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Freescale Semiconductor /MK61F15WS /DDR /CR41

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Interpret as CR41

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0P1RDCNT0RESERVED0 (00)RP10RESERVED0 (00)WP10RESERVED

RP1=00, WP1=00

Description

DDR Control Register 41

Fields

P1RDCNT

Port 1 Read command Count
RESERVED

Reserved
RP1

Read command priority Port 1

0 (00): Highest

1 (01): -----

2 (10): -----

3 (11): Lowest
RESERVED

Reserved
WP1

Write command priority Port 1

0 (00): Highest

1 (01): -----

2 (10): -----

3 (11): Lowest
RESERVED

Reserved

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data